Solutions Search - LTC2208 - 16-Bit, 130Msps ADC

Alternate Bit Polarity Reduces Digital Feedback in High Speed ADCs

Apr 2nd 2014
Click here for a list of high speed data converters with alternate bit polarity mode Digital feedback occurs when the high speed transitions at the outputs of a high speed ADC are coupled (either capacitely or inductively) through the ground plane back to the sensitive analog input, creating unwanted tones and impairing the ...

Internal Dither Improves High Speed ADC SFDR Performance

Mar 3rd 2014
Click here for a complete list of analog to digital converters with internal dither The LTC2208 is a 16-bit ADC with a very linear transfer function; however, at low input levels even slight imperfections in the transfer function will result in unwanted tones. Small errors in the transfer function are usually a result of ADC ...

A Short Course in PCB Layout for High-Speed ADCs

Derek Redmayne - Staff Scientist Mar 28th 2013
The intention here is to create the most concise layout guide ever.  This goes against our general philosophy of writing to minimize the number of phone calls.  This will likely generate a few phone calls because the reasons for the advice are not given.  They are the subject of a much longer document for those ...

Maximum SNR vs Clock Jitter

Clarence Mayott - Applications Engineer Mar 4th 2013
When designing the clock network for a high speed ADC one of the most critical parameters is jitter.  The amount of clock jitter will set the maximum SNR that you can achieve for a given input frequency.  Most modern high speed ADCs have about 80fs of jitter, and the encode clock of the ADC should be in that ball park.  ...