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Increase Spectral Resolution for the LTC2387-18 Demo Board - Part 2

Doug Stuetzle - Senior Analog Applications Engineer Oct 14th 2016


In Part 1 we designed and tested a lowpass + downsample structure that increased the spectral resolution of the DC2290A-A demonstration circuit for the LTC2387-18 high speed successive approximation register (SAR) ADC from 114Hz to 0.596Hz per bin. The average noise level per bin was also lowered by nearly 12dB.

The filter was implemented as a 128 word shift register and an adder. Following this with a downsampler used 74% of the available logic gates in the FPGA. This method allows the user to weight different taps as needed, at the expense of complexity. If there is no need to weight the taps, to add time windowing for example, then there is a way to drastically reduce the number of additions per sample.

The following refers to the LTC2387-18 but applies to all members of the LTC2387 family (LTC2386 & LTC2385) and to the other varients of the DC2290A demonstration circuits, the only difference being the sample rate and the number of bits.

A Simpler Approach

A simpler way to implement this filter is to load a N tap register one sample at a time, and then form the sum of all taps once. As each new sample arrives, it is added to the total and the earliest tap is subtracted from the total. In this way, we avoid summing all the taps every time a sample enters the shift register. Here is an example for N=128.

  1. First the FPGA deserializes the 18 bit data word.
  2. The word, along with a clock running at 15MHz, is passed to a module boxcar_128.

wire [17:0] dout, dout_f;
boxcar_128 box (

The first variable is the clock; the rising edge of this clock appears just after the deserialized data from the conversion is available. The next two variables are 18 bit data words, the first is the filter input and the second is the output. Here is the code for the module itself.

module boxcar_128 (

input clk;
input din;
output dout;

wire [17:0] din;
reg [17:0] dout;
reg [2321:0] shift_reg;
reg [24:0] sum_reg;

shift_reg = 0;
sum_reg = 0;

//load the shift register & update sum
always @ (posedge clk)
shift_reg = shift_reg << 18;
shift_reg[17:0] = din;
sum_reg = sum_reg + {{7{shift_reg[17]}},shift_reg[17:0]} - {{7{shift_reg[2321]}},shift_reg[2321:2304]};

//scale the output to 18 bits
always @ (negedge clk)
dout = {{7{sum_reg[24]}},sum_reg[24:7]};


The heart of the module is still shift_reg; this is a shift register that holds 128 x 18 bit words. Just as in the first version, these words are the data inputs din that are loaded into the shift register one after another. At each clock rising edge, the latest data word is loaded into the register and the oldest one is discarded. The sum of the 128 positions in the register is the output of the filter. This output is then scaled down by 7 bits to fit within an 18 bit word, and passed back to the main module as dout. At this point, the spectrum of these samples is just a lowpass filtered copy of the ADC output. Note again that, in this case, there is only one addition and one subtraction per sample. In Part 1 of this blog, 128 additions were performed per sample, which greatly increased the number of logic units required.

  1. The next step is downsampling, which is done by passing every 128th filter sample to the data collection board.

Comparison of Results

This structure yields the same noise levels and resolution as the more complex canonical implementation of Part 1, but uses only 3% of the available logic elements in the FPGA. It is much simpler because there is only one addition and one subtraction performed at each sample instant. Both the Verilog and programming files for the code described herein are available on the right hand panel.

FFT of the Filtered & Downsampled Signal65K Point FFT of a 9.76KHz Tone, Noise per Bin of -151.3dBFS




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