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Terasic DE0-Nano-SoC Kit / Atlas-SoC Kit

The DE0-Nano-SoC Development Kit presents a robust hardware design platform built around the Altera System-on-Chip (SoC) FPGA, which combines the latest dual-core Cortex-A9 embedded cores with industry-leading programmable logic for ultimate design flexibility. Users can now leverage the power of tremendous re-configurability paired with a high-performance, low-power processor system. Altera’s SoC integrates an ARM-based hard processor system (HPS) consisting of processor, peripherals and memory interfaces tied seamlessly with the FPGA fabric using a high-bandwidth interconnect backbone. The DE0-Nano-SoC development board is equipped with high-speed DDR3 memory, analog to digital capabilities, Ethernet networking, and much more that promise many exciting applications.

The DE0-Nano-SoC Development Kit contains all the tools needed to use the board in conjunction with a computer that runs the Microsoft Windows XP or later.

What's different between the DE0-Nano-SoC kit and the Atlas-SoC kit?

The hardware is the same for the DE0-Nano-SoC kit and the Atlas-SoC kit. The only difference is the getting-started process for the two kits. Users can freely use the DE0-Nano-SoC kit resources on the Atlas-SoC kit and vice versa.

DE0 Nano SoC Dev Platform (Top View)DE0 Nano SoC Dev Platform (Top View)

DE0 Nano SoC Dev Platform (Bottom View)DE0 Nano SoC Dev Platform (Bottom View)

DE0 Nano SoC Power TreeDE0 Nano SoC Power Tree


Function / Rail  Part Number General Description of Part

1.1 V: VCCINT (FPGA Core )

1.1V: HPS Core (FPGA Hardened Core)


LTC3612 3A, 4MHz Synchronous Step-Down DC/DC Convertor
1.5V: VCCIO LT3080 Adjustable 1.1A Single Resister Low Dropout Regulator
9V: HDR LT3580 Boost/Inverting DC/DC Converter with 2A Switch, Soft-Start, and Synchronozation

DE0 Nano SoC Block DiagramDE0 Nano SoC Block Diagram