# Transimpedance Amplifier Noise Considerations

The LTC6268 and LTC6269 is a single/dual 500MHz FET-input operational amplifier with extremely low input bias current and low input capacitance. It also features low input referred current noise and voltage noise making it an ideal choice for high speed transimpedance amplifiers, CCD output buffers, and high-impedance sensor amplifiers. Its low distortion makes the LTC6268/LTC6269 an ideal amplifier for driving SAR ADCs.

### Noise In Transimpedance Amplifiers

To minimize the LTC6268’s noise over a broad range of applications, careful consideration has been placed on input referred voltage noise (e_{N}), input referred current noise (i_{N}) and input capacitance C_{IN}.

For a trans-impedance amplifier (TIA) application such as shown in Figure 1, all three of these op amp parameters, plus the value of feedback resistance R_{F}, contribute to noise behavior in different ways, and external components and traces will add to C_{IN}.

It is important to understand the impact of each parameter independently. Input referred voltage noise (e_{N}) consists of flicker noise (or 1/f noise), which dominates at lower frequencies, and thermal noise which dominates at higher frequencies. For LTC6268, the 1/f corner, or transition between 1/f and thermal noise, is at 80kHz. The i_{N} and RF contributions to input referred noise current at the minus input are relatively straight forward, while the e_{N} contribution is amplified by the noise gain. Because there is no gain resistor, the noise gain is calculated using feedback resistor(R_{F}) in conjunction with impedance of C_{IN} as (1 + 2π R_{F} • C_{IN} • Freq), which increases with frequency. All of the contributions will be limited by the closed loop bandwidth. The equivalent input current noise is shown in Figures 2-5, where e_{N} represents contribution from input referred voltage noise (e_{N}), i_{N} represents contribution from input referred current noise (i_{N}), and R_{F} represents contribution from feedback resistor (R_{F}). TIA gain (R_{F}) and capacitance at input (C_{IN}) are also shown on each figure. Comparing Figures 2 & 3, and 4 & 5 for higher frequencies, e_{N} dominates when C_{IN} is high (5pF) due to the amplification mentioned above while iN dominates when C_{IN} is low (1pF).

At lower frequencies, the R_{F} contribution dominates for 10k and 100k. Since wide band e_{N} is 4.3nV/√Hz (see typical performance characteristics), R_{F} contribution will become a lesser factor at lower frequencies if R_{F} is less than 1.16kΩ as indicated by the following equation:

### Optimizing The Bandwidth For TIA Application

The capacitance at the inverting input node can cause amplifier stability problems if left unchecked. When the feedback around the op amp is resistive (R_{F}), a pole will be created with R_{F} ||C_{IN}. This pole can create excessive phase shift and possibly oscillation. Referring to Figure 1, the response at the output is:

Where R_{F} is the DC gain of the TIA, ω is the natural frequency of the closed loop, which can be expressed as:

ζ is the damping factor of the loop, which can be expressed as

Where C_{IN} is the total capacitance at the inverting input node of the op amp, and GBW is the gain bandwidth of the op amp. There are two regions that the system will be stable regardless of C_{F}. The first region is when R_{F} is less than 1/(4π∙C_{IN}∙GBW). In this region, the pole produced by the feedback resistor and C_{IN} is at a high frequency which does not cause stability problems. The second region is where:

Where A_{O} is the DC open loop gain of the op amp, and the pole formed by R_{F} C_{IN} is the dominant pole.

For R_{F} between these two regions, the small capacitor C_{F} in parallel with R_{F} can introduce enough damping to stabilize the loop. By assuming C_{IN} >> C_{F}, the following condition needs to be met for C_{F},

The above condition implies that higher GBW will require lower feedback capacitance C_{F}, which will have higher loop bandwidth. Table 1 shows the optimal C_{F} for R_{F} of 10kΩ and 100kΩ and C_{IN} of 1pF and 5pF.

### Achieving Higher Bandwidth With Higher Gain TIAs

Good layout practices are essential to achieving best results from a TIA circuit. The following two examples show drastically different results from an LTC6268 in a 499kΩ TIA. (See Figure 6.) The first example is with an 0603 resistor in a basic circuit layout. In a simple layout, without expending a lot of effort to reduce feedback capacitance, the bandwidth achieved is about 2.5MHz. In this case, the bandwidth of the TIA is limited not by the GBW of the LTC6268, but rather by the fact that the feedback capacitance is reducing the actual feedback impedance (the TIA gain itself) of the TIA. Basically, it’s a resistor bandwidth limitation. The impedance of the 499kΩ is being reduced by its own parasitic capacitance at high frequency. From the 2.5MHz bandwidth and the 499kΩ low frequency gain, we can estimate the total feedback capacitance as C = 1/(2π • 2.5MHz • 499kΩ) = 0.13pF. That’s fairly low, but it can be reduced further.

With some extra layout techniques to reduce feedback capacitance, the bandwidth can be increased. Note that we are increasing the effective “bandwidth” of the 499kΩ resistance. One of the main ways to reduce capacitance is to increase the distance between the plates, in this case the plates being the two endcaps of the component resistor. For that reason, it will serve our purposes to go to a longer resistor. An 0805 is longer than an 0603, but its endcaps are also larger in area, increasing capacitance again. However, increasing distance between the endcaps is not the only way to decrease capacitance, and the extra distance between the resistor endcaps also allows the easy application of another technique to reduce feedback capacitance. A very powerful method to reduce plate to plate capacitance is to shield the E field paths that give rise to the capacitance. In this particular case, the method is to place a short ground trace between the resistor pads, near the TIA output end.

Such a ground trace shields the output field from getting to the summing node end of the resistor and effectively shunts the field to ground instead. Keeping the trace close to the output end increases the output load capacitance very slightly. See Figure 8 for a pictorial representation.

Figure 9 shows the dramatic increase in bandwidth simply by careful attention to low capacitance methods around the feedback resistance. Bandwidth was raised from 2.5MHz to 11.2MHz, a factor greater than 4. Methods implemented were two:

- Minimal pad sizing. Check with your board assembler for minimum acceptable pad sizing, or assemble this resistor using other means, and
- Shield the feedback capacitance using a ground trace under the feedback resistor near the output side.