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LT3652 Solar Battery Charger Maintains High Efficiency in Low Light

Jay Celani - Staff Design Engineer Oct 31st 2013

An important characteristic of any solar panel is that it achieves peak power output at a relatively constant operating voltage (VMP) regardless of illumination level (see Figure 2). The LT3652 2A battery charger exploits this characteristic to maintain a solar panel at peak operating efficiency by implementing input voltage regulation (patent pending). When available solar power is inadequate to meet the power requirements of an LT3652 battery charger, input voltage regulation reduces the battery charge current. This reduces the load on the solar panel to maintain the panel voltage at VMP, maximizing the panel output power. This method of achieving peak panel efficiency is called maximum power point control (MPPC).

17V Vmp solar panel to 3-cell Li-Ion (12.6V) 2A chargerFigure 1. 17V VMP solar panel to 3-cell Li-ion (12.6V) 2A charger

Figure 2. A solar panel produces maximum power at a particular output voltage, VMP, which is relatively independent of illumination level. The LT3652 2A battery charger maximizes the output power of a solar panel by regulating the input panel voltage at VMP.

While MPPC optimizes solar panel efficiency during periods of low illumination, the power conversion efficiency of the battery charger suffers when power levels are low, degrading the overall power transfer efficiency from the panel to the battery. This article shows how to improve battery charger efficiency by applying a simple PWM charging technique that forces the battery charger to release energy in bursts when power levels are low.

USING THE CURRENT MONITOR STATUS PIN TO INDICATE LOW POWER CONDITIONS

The CHRG current monitor status pin on the LT3652 indicates the state of battery charge current, and is used here to control the PWM function. The pin is pulled low when the charger output current is greater than C/10, or 1/10 of the programmed maximum current, and high impedance when the output current is below C/10. During periods of low illumination, the input regulation loop can reduce the output current of the charger to below C/10, causing the CHRG pin to become high impedance. This status pin change-of-state is used to disable the IC by triggering an input undervoltage lockout (UVLO) with the falling threshold at a solar panel voltage that is higher than the input regulation voltage VIN(REG). The solar panel voltage climbs through the UVLO hysteresis range in response to the charger being disabled until the UVLO rising threshold is achieved, when the charger is re-enabled at full power. The charger then provides charge current until input voltage regulation again disables the charger. This cycle repeats, generating a charger output that is a series of high current bursts, which maximizes the efficiency of the charger as well as the efficiency of the entire solar charger system at any illumination level.

HIGH EFFICIENCY LI-ION CHARGER

Figure 1 shows a solar panel to 3-cell Li-Ion charger with low power PWM functionality. This charger employs a 17V input regulation voltage (a common VMP for “12V system” panels), programmed using the resistor divider R4 and R5 at the VIN_REG pin. Keeping the operating voltage of a typical 12V system solar panel near its 17V rated VMP voltage yields panel efficiencies close to 100%, as shown in Figure 3. The low power PWM function is implemented using M1, R6, R7 and R8.

12V System EfficiencyFigure 3. Typical “12V system” (VMP = 17V) solar panel efficiency

Figure 4 shows that the addition of the PWM circuitry significantly increases efficiency at battery charge currents below 200mA. The LT3652’s CHRG pin is pulled low while required charge current exceeds 1/10 of the 2A programmed maximum charge current, or 200mA. When charge current is reduced by the input regulation loop below the 200mA level, the CHRG pin becomes high impedance, which allows the gate of M1 to be pulled up to VBAT, enabling the FET, M1. This FET pulls R7 to ground, engaging an input voltage UVLO function using the SHDN pin and the resistor divider made from R6 and R7. The UVLO function is programmed with that divider to have a falling threshold of 18V and a rising threshold of 20V. The falling threshold is the critical design value, and must be programmed to a voltage that is higher than the input regulation voltage, and is 10% lower than the rising threshold, as is dictated by the LT3652 shutdown threshold hysteresis. During low illumination conditions, when available panel power is insufficient for the LT3652 to provide required charge current, the LT3652’s input voltage regulation reduces the output charge current until the charger input power is equivalent to the available power provided by the panel. With input regulation active, the panel voltage at VIN is held at the programmed 17V peak power voltage, maximizing the power produced from the panel. If the panel illumination becomes low enough that the available panel power corresponds to charge current less than 200mA, the CHRG pin becomes high impedance and the UVLO function is enabled via M1, R6 and R7.

LT3652 Circuit EfficiencyFigure 4. Efficiency for the circuit in Figure 2

Since VIN is at 17V, which is lower than the UVLO falling threshold, the LT3652 shuts down, disabling all of the battery charging functions. With the battery charger disabled, virtually all of the panel output current charges the input capacitor (C1), increasing the voltage at VIN until the 20V UVLO rising threshold is achieved, re-enabling the LT3652. The battery charger is re-enabled with VIN well above the 17V input regulation threshold, so full charge current flows into the battery. The CHRG status pin is pulled low in response to the high battery charge current level, which disables the UVLO function. As long as the power required by the battery charger remains less than that available from the solar panel, the panel voltage will collapse until VIN is reduced to 17V, when the battery charge current is reduced by input regulation to maintain that voltage. When the charge current is again reduced to 200mA, the CHRG pin becomes high impedance, the UVLO circuit is reengaged, and the disable/enable cycle repeats, resulting in a string of charge current ‘bursts’ that average to the battery charge current corresponding to the available power from the solar panel.

Figure 5 shows the PWM operation of the circuit in Figure 2. While the LT3652 is disabled, the voltage on VIN ramps from the input regulation threshold of 17V to the shutdown threshold of 20V. The voltage on the LT3652 CHRG pin is low while the charger is enabled and high while the charger is disabled. While the charger is disabled, the panel energy is stored in the input capacitor, so the output power from the panel remains continuous. The efficiency of the solar panel corresponds to the average voltage on the panel during PWM operation, which is about 18.5V.

LT3652 Vin WaveformFigure 5. Waveform of VIN during PWM for the circuit in Figure 2

For more circuits and examples of high efficiency solar battery charging applications, refer to the LT Journal article "Solar Battery Charger Maintains High Efficiency in Low Light".