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ADC Drivers & Filters: Single Ended Buffer

Guy Hoover - Applications Engineer Aug 28th 2013

Figure 1 shows a recommended single ended buffered drive circuit using the LT1818 in unity gain mode. The 47pF capacitor from AIN to ground and 50Ω source resistor limits the input bandwidth to 68MHz. The 47pF capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the LT1818 from sampling glitch kick-back. The 50Ω source resistor is used to help stabilize the settling response of the drive amplifier. When choosing values of source resistance and shunt capacitance, the drive amplifier data sheet should be consulted and followed for optimum settling response. If lower input bandwidths are desired, care should be taken to optimize the settling response of the driver amplifier with higher values of shunt capacitance or series resistance. High quality capacitors and resistors should be used in the RC filter since these components can add distortion. NP0/C0G and silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems. When high amplitude unwanted signals are close in frequency to the desired signal frequency, a multiple pole filter is required. High external source resistance, combined with external shunt capacitance at Pin 4 and 13pF of input capacitance on the LTC2314-14 in sample mode, will significantly reduce the internal 130MHz input bandwidth and may increase the required acquisition time beyond the minimum acquisition time (tACQ-MIN) of 40ns.

ADC Drivers & Filters: Single Ended Buffer Figure 1. RC Input Filter