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Dust Networks – LTC5800-IPR Demonstration Circuit with External Memory

Dust Networks – LTC5800-IPR Demonstration Circuit with External Memory

The LTC5800-IPR demonstration circuit is an example of integrating the LTC5800-IPR (QFN) Manager-on-Chip with external SRAM.  The additional memory the external SRAM provides enables SmartMesh IP managers with 100-mote capacity to support networks of more than 32 motes and increases the manager’s packet throughput. Please see the section titled “External Memory Support” in the Eterna Integration Guide for details on using external SRAM as well as design, layout, EMI, device configuration and manufacturing considerations.

 This reference design illustrates best practices for RF Antenna connection, crystal integration and power supply filtering. It is applicable to the LTC5800-IPR SmartMesh IP Manager-on-Chip.

 Design Files – Zip file that includes Schematics and BOM for the LTC5800-IPR Demonstration Circuit