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Timing
Clock Generation and Distribution
Clock Generation and Distribution
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Number of Outputs
Max Frequency
Input Span
Noise Floor
Jitter
Output
Comments
Packages
Units
MHz
dBc/Hz
ps
Selection
(hold Ctrl key to select multiple,
hold Shift key to select range)
2
3
5
300
1400
1800
2500
2700
0.2 to 2.0Vpp
0.2Vpp to 1.5Vpp
0.8 to 1.5Vpp
-168
-165
-161
-159.5
-155
0.018
0.02
0.045
0.053
0.067
0.115
1X LVDS/CMOS
1X LVPECL
1x LVDS
1x LVDS/CMOS
2X LVPECL
2XLVDS/CMOS outputs
3X LVDS/CMOS
3X LVPECL
4x CML
4x LVPECL
Complementary CMOS
In Phase CMOS
LVDS
LVPECL
1.4GHz Low Phase Noise, Low Jitter PLL with Clock Distribution
Low Phase Noise, Dual Output Buffer/Driver/Logic Converter, CMOS Logic, Complementary Outputs
Low Phase Noise, Dual Output Buffer/Driver/Logic Converter, CMOS Logic, In-Phase Outputs
Low Phase Noise, Dual Output Buffer/Driver/Logic Converter, LVDS Logic Outputs
Low Phase Noise, Dual Output Buffer/Driver/Logic Converter, LVPECL Logic Outputs
Low Phase Noise, Triple Output Clock Distribution Divider/Driver, One LVPECL and two LVDS/CMOS outputs
Low Phase Noise, Triple Output Clock Distribution Divider/Driver, Three LVDS/CMOS outputs
Low Phase Noise, Triple Output Clock Distribution Divider/Driver, Three LVPECL outputs
Low Phase Noise, Triple Output Clock Distribution Divider/Driver, Two LVPECL and one LVDS/CMOS
Ultralow Jitter Multi-Output Clock Synthesizer with Integrated VCO
3x3 DFN-12
4x7 QFN-36
5x7 QFN-40
5x9 QFN-48
MS-12
LTC6957-3
2
300
0.2 to 2.0Vpp
-161
0.053
In Phase CMOS
Low Phase Noise, Dual Output Buffer/Driver/Logic Converter, CMOS Logic, In-Phase Outputs
3x3 DFN-12,MS-12
LTC6957-1
2
300
0.2 to 2.0Vpp
-161
0.045
LVPECL
Low Phase Noise, Dual Output Buffer/Driver/Logic Converter, LVPECL Logic Outputs
3x3 DFN-12,MS-12
LTC6957-2
2
300
0.2 to 2.0Vpp
-159.5
0.067
LVDS
Low Phase Noise, Dual Output Buffer/Driver/Logic Converter, LVDS Logic Outputs
3x3 DFN-12,MS-12
LTC6954-4
3
1400
0.2Vpp to 1.5Vpp
-168
0.02
3X LVDS/CMOS
Low Phase Noise, Triple Output Clock Distribution Divider/Driver, Three LVDS/CMOS outputs
4x7 QFN-36
LTC6957-4
2
300
0.2 to 2.0Vpp
-161
0.053
Complementary CMOS
Low Phase Noise, Dual Output Buffer/Driver/Logic Converter, CMOS Logic, Complementary Outputs
3x3 DFN-12,MS-12
LTC6954-3
3
1400
0.2Vpp to 1.5Vpp
-168
0.02
1X LVPECL, 2XLVDS/CMOS outputs
Low Phase Noise, Triple Output Clock Distribution Divider/Driver, One LVPECL and two LVDS/CMOS outputs
4x7 QFN-36
LTC6951
5
2500
0.8 to 1.5Vpp
-165
0.115
4x CML, 1x LVDS
Ultralow Jitter Multi-Output Clock Synthesizer with Integrated VCO
5x7 QFN-40
LTC6951-1
5
2700
0.8 to 1.5Vpp
-165
0.115
4x CML, 1x LVDS
Ultralow Jitter Multi-Output Clock Synthesizer with Integrated VCO
5x7 QFN-40
LTC6954-1
3
1800
0.2Vpp to 1.5Vpp
-168
0.02
3X LVPECL
Low Phase Noise, Triple Output Clock Distribution Divider/Driver, Three LVPECL outputs
4x7 QFN-36
LTC6954-2
3
1400
0.2Vpp to 1.5Vpp
-168
0.02
2X LVPECL, 1X LVDS/CMOS
Low Phase Noise, Triple Output Clock Distribution Divider/Driver, Two LVPECL and one LVDS/CMOS
4x7 QFN-36
LTC6950
5
1400
0.8 to 1.5Vpp
-155
0.018
4x LVPECL, 1x LVDS/CMOS
1.4GHz Low Phase Noise, Low Jitter PLL with Clock Distribution
5x9 QFN-48