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Clarence Mayott - Applications Engineer

Clarence Mayott is a mixed signal application section leader with over 10 year experience at Linear Technology.

Beginning with the DC1151, a demo board for the LTC2246H, Clarence has designed nearly all of the high speed ADC demo boards for Linear Technology. These boards have been used for evaluation purposes in a wide range of applications. He designed demo boards with complete signal chains combining amplifiers and ADC combinations to help the end customer evaluate systems more easily. He also designed companion boards, including clock and signal source boards, to help facilitate the evaluation of high speed ADC demo boards. Clarence manages the continued development of PScope, the software used for various pipeline and SAR ADCs.

His expertise in design and layout of demo boards allows him to instruct customers on how to implement high speed ADCs into their own designs. He has worked on many technical areas, including medical, automotive and communications. His experience allows him to see schematic errors, minute layout errors, and other design flaws in designs.

With the release of the LTC2000, Clarence has expanded his knowledge base to include high speed DACs and waveform generation in addition to high speed ADCs. As an application section leader he oversees the continued development of LTDACGen a new software tool for generating complex waveforms for high speed DACs.

He has given technical trainings both within Linear Technology and to potential customers describing how to implement proper signal chains from the antenna through the FPGA.

He received an M.S. in Electrical Engineering from Santa Clara University and a B.S. degree in Electrical Engineering from California State University Polytechnic San Luis Obispo.


Type Title Date ▴
Blog Improving Linearity by Using Absorptive Filters Mar 10th, 2017
Blog Uncompromised Linearity from the LTC2185 and ADA4927-1 Mar 10th, 2017
Blog Uncompromised Clocking Solution for 16-Bit 2.5Gsps High Performance DAC Sep 6th, 2016
Blog Using the Averaging Functions of PScope Jul 18th, 2016
Video High Speed DAC for Wide Bandwidth Signal Generation Aug 25th, 2014
Blog Coherent Sampling with PScope Nov 22nd, 2013
Blog PScope Basics Nov 8th, 2013
Design Note DN1031 - Interfacing to High Performance Pipeline ADCs Jun 21st, 2013
Blog Maximum SNR vs Clock Jitter Mar 4th, 2013
Blog Get a 3dB SNR Boost Using a Dual ADC Mar 4th, 2013
Video PScope: High-Speed ADC Data Collection Software Jan 4th, 2011
LT Journal December 2009 - Maximize the Performance of 16-Bit, 105Msps ADC with Careful IF Signal Chain Design Dec 1st, 2009
LT Journal December 2009 - New Generation of 14-Bit 150Msps ADCs Dissipates a Third the Power of the Previous Generation without Sacrificing AC Performance Dec 1st, 2009
Design Note DN468 - Maximize the Performance of 16-Bit, 105Msps ADC with Careful IF SIgnal Chain Design May 30th, 2009
Video Reduce Digital Feedback in High Speed Data Conversion Systems - LTC2261 Mar 15th, 2009
LT Journal September 2008 - Serial Interface for High Speed Data Converters Simplifies Layout over Traditional Parallel Devices Sep 23rd, 2008